The present invention relates to a floating-point arithmetic system, and mcre particularly to such a system formed of a semiconductor integrated circuit.
Processing of floating-point numbers has not been standardized, so that demand for execution of classification of floating-point numbers in terms of their attributes (zero, infinity, not-a-number, normalized number, and denormalized number) by hardware has not been strong. But recently, an IEEE (The Institute of Electrical and Electronics Engineers, Inc.) Standard concerning processing of floating-point numbers was proposed, and the need for processing in accordance with the classification of the floating-point numbers has arisen.
Conventional floating-point arithmetic units generally comprise a floating-point processor under microprogram control. The classification of the input operands is often done by a microprogram. Similarly, exception handling in accordance with the classification in terms of the attribute is often done by a microprogram.
Where the classification of the operands is done by a microprogram, at least one machine cycle is necessary to execute the classification. Moreover, a number of machine cycles are needed for the exception handling. As a result, the processing by the conventional system is slow.